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  ·05-25
  这篇文章不错，转发给大家看看
  2031年等效1.4纳米，华为提出的韬定律到底是什么？
  　　5月25日，在上海举行的国际电路与系统研讨会这一汇聚全球顶尖半导体学者的学术盛会上，华为公司董事、半导体业务部总裁何庭波发表题为《半导体新路径探索与实践》的主旨演讲，正式发布“韬（τ）定律”。　　但在讨论“韬定律”到底说了什么之前，有一个问题必须回答：好好的，为什么需要一个“新”定律？　　具体来说，当制程逼近2纳米、1纳米，一个原子就是一个“台阶”。
  2031年等效1.4纳米，华为提出的韬定律到底是什么？
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11:58","market":"sg","language":"zh","title":"2031年等效1.4纳米，华为提出的韬定律到底是什么？","url":"https://stock-news.laohu8.com/highlight/detail?id=2638876755","media":"观察者网","summary":"　　5月25日，在上海举行的国际电路与系统研讨会这一汇聚全球顶尖半导体学者的学术盛会上，华为公司董事、半导体业务部总裁何庭波发表题为《半导体新路径探索与实践》的主旨演讲，正式发布“韬（τ）定律”。　　但在讨论“韬定律”到底说了什么之前，有一个问题必须回答：好好的，为什么需要一个“新”定律？　　具体来说，当制程逼近2纳米、1纳米，一个原子就是一个“台阶”。","content":"<html><body><div>\n<div><img src=\"http://n.sinaimg.cn/spider20260525/641/w1080h361/20260525/4700-c510f5ed69312a0ea7c04b676fc9352c.jpg\"/><span></span></div>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L strong-Bold color330\">► 文 观察者网心智观察所</font></p>\n<p cms-style=\"font-L\">　　5月25日，在上海举行的国际电路与系统研讨会（ISCAS 2026）这一汇聚全球顶尖半导体学者的学术盛会上，华为公司董事、半导体业务部总裁何庭波发表题为《半导体新路径探索与实践》的主旨演讲，正式发布“韬（τ）定律”。</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">这是中国第一次在全球半导体领域提出指导产业发展的新原则，是一整套关于芯片性能到底该怎么持续提升的</font><font cms-style=\"font-L strong-Bold color330\">全新理论框架</font><font cms-style=\"font-L\">。</font></p>\n<p cms-style=\"font-L\">　　但在讨论“韬定律”到底说了什么之前，有一个问题必须回答：好好的，为什么需要一个“新”定律？</p>\n<p cms-style=\"font-L\">　　这又要回到一个所有人都知道、但很少有人真正理解的困境：摩尔定律，真的不行了吗？</p>\n<div><img src=\"http://n.sinaimg.cn/spider20260525/35/w831h804/20260525/9acf-e883e614e31ba79ff13cadae995281ac.jpg\"/><span></span></div>\n<p cms-style=\"font-L strong-Bold align-Center\">　　“韬定律”转变了什么思路？</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">其实，问题不在于摩尔定律本身“死了”，而在于它赖以运行的逻辑“几何缩微”</font><font cms-style=\"font-L strong-Bold color330\">到了物理极限。</font></p>\n<p cms-style=\"font-L\">　　过去半个多世纪，芯片产业的规则很简单：把晶体管尺寸越做越小，同等面积上堆更多器件，性能就能自动提升、功耗就能自动下降、成本就能自动摊薄。这套逻辑在几十纳米节点上都还跑得通，但从几十纳米走到几纳米，每一步的物理难度和工程成本都在指数级膨胀。</p>\n<p cms-style=\"font-L\">　　具体来说，当制程逼近2纳米、1纳米，一个原子就是一个“台阶”。量子隧穿效应开始捣乱，电子会在不该跑的地方“穿墙漏电”。电流越来越难控制，功耗散热成了烫手山芋。建厂成本则越来越高，一座3nm晶圆厂动辄200亿美元起步，全球玩得起的玩家从几十家缩到了三四家。</p>\n<p cms-style=\"font-L\">　　一边是微缩的边际收益急剧递减，一边是AI、大模型、自动驾驶对算力呈指数级攀升的胃口。这个剪刀差，就是华为“韬定律”试图回答的根本问题。</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">何庭波的答案是：</font><font cms-style=\"font-L strong-Bold color330\">别再死盯着“尺寸”，开始盯着“时间”。</font></p>\n<p cms-style=\"font-L\">　　这就是“韬定律”最核心的转变：以“时间缩微”替代“几何缩微”。</p>\n<p cms-style=\"font-L strong-Bold align-Center\">　　“韬定律”的四个层级优化</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">“时间缩微”听起来有点抽象，但拆开来看并不复杂。在半导体的世界里，芯片的性能和晶体管密度，最终是由一个叫“时间常数τ”（希腊字母τ，中文发音“韬”）的东西决定的。它代表</font><font cms-style=\"font-L strong-Bold color330\">信号在芯片里从一个地方跑到另一个地方所需要的时间。</font><font cms-style=\"font-L\">信号跑得越快、路径越短、延迟越低，单位时间内能处理的数据就越多，芯片的晶体管密度和性能自然也越高。</font></p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">过去，业界提升性能的思路是“把晶体管做得更小”，这样走线就能更密、信号不用跑太远。华为的思路则是：</font><font cms-style=\"font-L strong-Bold color330\">在不显著缩小晶体管尺寸的前提下，通过系统性地压缩信号传播时延，来实现同样的效果。</font></p>\n<p cms-style=\"font-L\">　　这个思路听起来有点像在上下班高峰期，不去扩建道路（扩宽尺寸），而是想办法优化红绿灯、设置潮汐车道、加修高架和地下通道，把交通流理顺了，车速自然就提上来了。</p>\n<p cms-style=\"font-L\">　　华为实现这个思路的核心技术，叫“逻辑折叠”。</p>\n<p cms-style=\"font-L\">　　传统芯片的电路布局是二维平面上的，信号在平面上左冲右突，很多时间花在了走线上。逻辑折叠的本质，是把电路布局从“一层楼”扩展成“多层楼”，把原本需要长距离横向走线的关键路径“折”起来，纵向叠放，从而大幅缩短信号传播的物理距离。</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">而逻辑折叠只是华为多层级协同体系中的一个关键抓手。从华为此前公布的技术路线图来看，“韬定律”构建了一个贯穿</font><font cms-style=\"font-L strong-Bold color330\">器件、电路、芯片到系统</font><font cms-style=\"font-L\">的四层级优化体系。</font></p>\n<p cms-style=\"font-L\">　　在最底层的器件层面，华为从优化晶体管的电阻、寄生电容入手，从物理底层最大限度压缩时间常数τ，打好地基。</p>\n<p cms-style=\"font-L\">　　在电路层面，逻辑折叠技术突破传统平面布局的物理边界，把电路从单层“折”成双层乃至多层。</p>\n<p cms-style=\"font-L\">　　在芯片层面，华为引入“软件、架构、芯片”的全栈协同设计，基于实际工作负载去调配指令流和数据流，让芯片只算必须算的东西，减少无效开销，把端到端的执行时间压到最低。</p>\n<p cms-style=\"font-L\">　　在最顶层的系统层面，华为还定义了“灵衢总线”，重构计算系统互联协议，实现“超节点统一内存编址和原生内存语义”，让数据在不同计算单元之间来回交换时几乎不再有“堵车”的感觉。</p>\n<p cms-style=\"font-L\">　　这四个层级不是一个一个去优化的线性组合，而是像齿轮一样咬合在一起。如果打个比方，传统的芯片优化路径，就像在一条越来越窄的窄路上拼命堆砌跑车。而“韬定律”把整个路线图拉到了更宽的维度上：器件、电路、芯片、系统协同演进，信号跑得更快、算得更聪明。</p>\n<p cms-style=\"font-L strong-Bold align-Center\">　　“韬定律”的高端芯片目标</p>\n<p cms-style=\"font-L\">　　“韬定律”能不能成立，最终看产品。</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">何庭波在演讲中提供了一个关键数字：过去六年，华为基于这条路径已成功设计并量产了</font><font cms-style=\"font-L strong-Bold color330\">381款芯片</font><font cms-style=\"font-L\">，覆盖通信、计算、终端、车载等各个领域。这是华为“韬定律”理论能够站住脚的重要底气。</font></p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">真正让市场期待的，是今年秋天即将发布的新一代麒麟手机芯片。按何庭波的说法，这颗芯片将</font><font cms-style=\"font-L strong-Bold color330\">完整采用逻辑折叠技术</font><font cms-style=\"font-L\">，基于全新的自由逻辑设计理念，由单层扩展至双层，实现晶体管密度和系统性能的大幅跃升。</font></p>\n<p cms-style=\"font-L\">　　何庭波的原话是：“我们取得了一系列仅靠先进制程工艺难以取得的进步。”这可能意味着华为走通了一条不同于<a href=\"https://laohu8.com/S/TSM\">台积电</a>、<a href=\"https://laohu8.com/S/SMSN.UK\">三星</a>、<a href=\"https://laohu8.com/S/INTC\">英特尔</a>的独立路线。</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">她还透露了一个更长远的目标：到2031年，基于“韬定律”的高端芯片，晶体管密度将达到</font><font cms-style=\"font-L strong-Bold color330\">1.4纳米制程</font><font cms-style=\"font-L\">的同等水平。这意味着华为将通过系统级的时间优化，实现与1.4nm工艺同等的集成密度和计算能力。</font></p>\n<p cms-style=\"font-L\">　　这到底是不是一条走得通的路线？何庭波的原话是：“我们的解决方案走得通，走得远。我们新芯片的性能完全可以持续对标另外一条路径。”</p>\n<p cms-style=\"font-L strong-Bold align-Center\">　　全球半导体产业的新技术浪潮</p>\n<p cms-style=\"font-L\">　　如果“韬定律”可以被理解为从“空间”转向“时间”的范式转移，那么全球半导体产业的另一条主线，就是从“平面”走向“立体”。</p>\n<p cms-style=\"font-L\">　　有趣的是，这两条线正在同一时间点上交汇。</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">以先进封装、Chiplet异构集成和混合键合为代表的技术浪潮，正在以前所未有的速度和规模重塑芯片的性能边界。它们与“韬定律”的核心思路异曲同工：</font><font cms-style=\"font-L strong-Bold color330\">不依赖晶体管本身的无限微缩，而是通过更聪明的集成和互连方式，推动系统级性能的持续跃升。</font></p>\n<p cms-style=\"font-L\">　　先看先进封装。如果说过去几十年，业界讨论“几纳米”就是讨论芯片的一切，那么从2024到2026年，讨论话题的重心正在快速向先进封装倾斜。根据Yole Group的数据，2025年全球先进封装市场规模约531亿美元，预计到2030年有望达到794亿美元，年复合增长率约8.4%。更令人吃惊的是2.5D/3D封装的增长速度：2023年至2029年间，其年复合增长率高达37%。</p>\n<p cms-style=\"font-L\">　　为什么涨得这么快？原因简单粗暴：AI芯片需求爆了。以台积电CoWoS为代表的先进封装，把GPU核心和高带宽内存（HBM）紧贴在一起，信号传输距离从毫米级压缩到微米级，是AI大模型时代算力爆炸的“隐形底座”。数据显示，目前全球2.5D与3D先进封装产能仍供不应求，部分订单从下单到交货甚至超过一年，供应缺口高达约23%。全球头部厂商正在掀起扩产狂潮：台积电计划布局七座先进封装工厂，规划到2027年将年产能从130万片提升到200万片，增幅约53.85%。</p>\n<p cms-style=\"font-L\">　　再看Chiplet（芯粒）。这项技术背后的逻辑是把一颗超大芯片拆成多个小芯粒，各自用最优制程做出来，再通过先进封装“粘”在一起，有点像“把一块大棋盘切成几块小拼图再拼回去”。Chiplet架构在AI芯片中已经大面积铺开，尤其对于国内芯片厂商来说，这项技术更具战略意义：它允许部分核心模块使用先进制程，而非关键的I/O、存储模块用成熟制程，有效弥补了先进制程受限的短板，实现了“用有限资源换系统级性能”。</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">如果说Chiplet是“搭积木”，那</font><font cms-style=\"font-L strong-Bold\">混合键合</font><font cms-style=\"font-L\">就是决定这些积木能不能搭得稳、搭得密的那把“胶水”。混合键合的突破性在于：它完全不需要焊料凸块，直接让铜和铜在原子层级接触，实现芯片间铜-铜和氧化物-氧化物的直接键合。相比传统热压键合，混合键合带来的互连密度能提升一到两个数量级，寄生电容极低，信号延迟和功耗都大幅下降。</font></p>\n<p cms-style=\"font-L\">　　这项技术被业界视为“后摩尔时代未来十年的必选技术路线”。从具体落地看，存储巨头们已经集体杀入。SK海力士和三星都在为下一代HBM高带宽内存铺路，预计混合键合将从HBM4开始引入，16层HBM的堆叠结构正在紧锣密鼓地验证中。混合键合设备市场的年复合增长率预计高达69%，远超半导体行业的整体增速。</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">还有一个更前沿的方向：</font><font cms-style=\"font-L strong-Bold color330\">硅光互连与<a href=\"https://laohu8.com/S/600184\">光电</a>共封装（CPO）。</font></p>\n<p cms-style=\"font-L\">　　信号传输的本质瓶颈，正在从芯片内部向芯片之间、乃至机柜之间的互连转移。传统的铜互连在高频率下损耗大、距离有限，越来越撑不住大规模AI集群的带宽需求。硅光互连的核心思路是用光代替电来传信号，速度更快、延迟更低、功耗大幅下降。</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">台积电在2026年5月的技术论坛上高调披露了其</font><font cms-style=\"font-L strong-Bold color330\">“三层蛋糕”AI平台架构</font><font cms-style=\"font-L\">：底层是运算层（Compute），中间是封装集成层（CoWoS/SoIC），最顶层是“未来最重要的”光子互连层（COUPE）。COUPE技术通过3D异质集成方式，将电子芯片与光子芯片垂直堆叠，使得组件之间距离极近，大幅降低电耦合损耗。据台积电透露，今年已启动全球首款采用COUPE技术的200Gbps微环调制器的量产，比特误码率低于一亿分之一。相比传统铜线，COUPE可使系统能效提升4倍、延迟降低10倍；若与封装平台深度整合，能效甚至可提升到10倍，延迟降低20倍。</font></p>\n<p cms-style=\"font-L\">　　<span><a href=\"https://laohu8.com/S/600109\">国金证券</a></span><span></span>在最新研报中明确指出：2026年是CPO的产业化元年。台积电、<a href=\"https://laohu8.com/S/NVDA\">英伟达</a>、<a href=\"https://laohu8.com/S/AVGO\">博通</a>等产业链核心玩家已经跑步进场，标志着“光进铜退”在AI数据中心的大规模落地正式拉开帷幕。</p>\n<p cms-style=\"font-L strong-Bold align-Center\">　　结语</p>\n<p cms-style=\"font-L\">　　<font cms-style=\"font-L\">往长期看，华为“韬定律”与整个产业技术演进的方向是高度一致的。不论叫“时间缩微”还是叫“先进封装”，背后的本质都是一个根本性的共识判断：</font><font cms-style=\"font-L strong-Bold color330\">芯片性能的提升，不能再只依赖“把晶体管做小”。</font></p>\n<p cms-style=\"font-L\">　　真正的竞争正在转移到一组新的维度上：互连密度、信号延迟、系统协同、垂直堆叠、光互连。这些维度的组合效应，远比单纯缩小一个节点要复杂、也要广阔得多。用华为自己的话说，2026年到2035年，随着大量探索性技术的逐步产品化，晶体管的密度将持续提升，工作频率将持续增长，高性能芯片源源不断。</p>\n<p cms-style=\"font-L\">　　何庭波在演讲的结尾，说了一句意味深长的话：“未来一定属于开放合作。在半导体演进的路径上，没有一家企业可以独自完成所有答案。在‘韬定律’的路径下，我们期待与全球科学家、工程师和产业伙伴紧密合作，共同推动半导体与电子产业持续发展。”</p>\n<p cms-style=\"font-L\">　　芯片产业链太长、太复杂，没有一个国家、一家公司能包揽全链条。包括光刻机在内的半导体设备、封装基板的材料、EDA工具、CPO的标准体系……每一环都需要全球协作。华为提出“韬定律”，是在半导体行业寻找全新增长曲线的关键时刻，为世界提供一种兼容、开放、可供选择的中国方案。</p>\n<div>\n<div><img src=\"\"/></div>\n<div>海量资讯、精准解读，尽在新浪财经APP</div>\n</div>\n<p>责任编辑：凌辰 </p>\n</div></body></html>","source":"sina","collect":0,"html":"<!DOCTYPE html>\n<html>\n<head>\n<meta http-equiv=\"Content-Type\" content=\"text/html; charset=utf-8\" />\n<meta name=\"viewport\" content=\"width=device-width,initial-scale=1.0,minimum-scale=1.0,maximum-scale=1.0,user-scalable=no\"/>\n<meta name=\"format-detection\" content=\"telephone=no,email=no,address=no\" />\n<title>2031年等效1.4纳米，华为提出的韬定律到底是什么？</title>\n<style type=\"text/css\">\na,abbr,acronym,address,applet,article,aside,audio,b,big,blockquote,body,canvas,caption,center,cite,code,dd,del,details,dfn,div,dl,dt,\nem,embed,fieldset,figcaption,figure,footer,form,h1,h2,h3,h4,h5,h6,header,hgroup,html,i,iframe,img,ins,kbd,label,legend,li,mark,menu,nav,\nobject,ol,output,p,pre,q,ruby,s,samp,section,small,span,strike,strong,sub,summary,sup,table,tbody,td,tfoot,th,thead,time,tr,tt,u,ul,var,video{ font:inherit;margin:0;padding:0;vertical-align:baseline;border:0 }\nbody{ font-size:16px; line-height:1.5; color:#999; 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class=\"title\">\n2031年等效1.4纳米，华为提出的韬定律到底是什么？\n</h2>\n\n<h4 class=\"meta\">\n\n\n2026-05-25 11:58 北京时间&nbsp;&nbsp;&nbsp;<a href=https://finance.sina.com.cn/wm/2026-05-25/doc-inhzasck5819281.shtml><strong>观察者网</strong></a>\n\n\n</h4>\n\n</header>\n<article>\n<div>\n<p>► 文 观察者网心智观察所\n　　5月25日，在上海举行的国际电路与系统研讨会（ISCAS 2026）这一汇聚全球顶尖半导体学者的学术盛会上，华为公司董事、半导体业务部总裁何庭波发表题为《半导体新路径探索与实践》的主旨演讲，正式发布“韬（τ）定律”。\n　　这是中国第一次在全球半导体领域提出指导产业发展的新原则，是一整套关于芯片性能到底该怎么持续提升的全新理论框架。\n　　但在讨论“韬定律”到底说了什么...</p>\n\n<a href=\"https://finance.sina.com.cn/wm/2026-05-25/doc-inhzasck5819281.shtml\">网页链接</a>\n\n</div>\n\n\n</article>\n</div>\n</body>\n</html>\n","type":0,"thumbnail":"","relate_stocks":{"LU2420271590.USD":"ALLIANZ SELECT INCOME AND GROWTH \"AT\" (USD) ACC","LU2065171311.SGD":"M&G (LUX) GLOBAL MAXIMA \"A\" (SGD) ACC","LU2505996509.AUD":"WELLINGTON MULTI-ASSET HIGH INCOME \"AM4H\" (AUDHDG) INC","LU2552382215.SGD":"WELLINGTON US BRAND POWER \"A\" (SGDHDG) ACC","LU2065171402.SGD":"M&G (LUX) GLOBAL MAXIMA \"A\" (SGD) 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2026）这一汇聚全球顶尖半导体学者的学术盛会上，华为公司董事、半导体业务部总裁何庭波发表题为《半导体新路径探索与实践》的主旨演讲，正式发布“韬（τ）定律”。\n　　这是中国第一次在全球半导体领域提出指导产业发展的新原则，是一整套关于芯片性能到底该怎么持续提升的全新理论框架。\n　　但在讨论“韬定律”到底说了什么之前，有一个问题必须回答：好好的，为什么需要一个“新”定律？\n　　这又要回到一个所有人都知道、但很少有人真正理解的困境：摩尔定律，真的不行了吗？\n\n　　“韬定律”转变了什么思路？\n　　其实，问题不在于摩尔定律本身“死了”，而在于它赖以运行的逻辑“几何缩微”到了物理极限。\n　　过去半个多世纪，芯片产业的规则很简单：把晶体管尺寸越做越小，同等面积上堆更多器件，性能就能自动提升、功耗就能自动下降、成本就能自动摊薄。这套逻辑在几十纳米节点上都还跑得通，但从几十纳米走到几纳米，每一步的物理难度和工程成本都在指数级膨胀。\n　　具体来说，当制程逼近2纳米、1纳米，一个原子就是一个“台阶”。量子隧穿效应开始捣乱，电子会在不该跑的地方“穿墙漏电”。电流越来越难控制，功耗散热成了烫手山芋。建厂成本则越来越高，一座3nm晶圆厂动辄200亿美元起步，全球玩得起的玩家从几十家缩到了三四家。\n　　一边是微缩的边际收益急剧递减，一边是AI、大模型、自动驾驶对算力呈指数级攀升的胃口。这个剪刀差，就是华为“韬定律”试图回答的根本问题。\n　　何庭波的答案是：别再死盯着“尺寸”，开始盯着“时间”。\n　　这就是“韬定律”最核心的转变：以“时间缩微”替代“几何缩微”。\n　　“韬定律”的四个层级优化\n　　“时间缩微”听起来有点抽象，但拆开来看并不复杂。在半导体的世界里，芯片的性能和晶体管密度，最终是由一个叫“时间常数τ”（希腊字母τ，中文发音“韬”）的东西决定的。它代表信号在芯片里从一个地方跑到另一个地方所需要的时间。信号跑得越快、路径越短、延迟越低，单位时间内能处理的数据就越多，芯片的晶体管密度和性能自然也越高。\n　　过去，业界提升性能的思路是“把晶体管做得更小”，这样走线就能更密、信号不用跑太远。华为的思路则是：在不显著缩小晶体管尺寸的前提下，通过系统性地压缩信号传播时延，来实现同样的效果。\n　　这个思路听起来有点像在上下班高峰期，不去扩建道路（扩宽尺寸），而是想办法优化红绿灯、设置潮汐车道、加修高架和地下通道，把交通流理顺了，车速自然就提上来了。\n　　华为实现这个思路的核心技术，叫“逻辑折叠”。\n　　传统芯片的电路布局是二维平面上的，信号在平面上左冲右突，很多时间花在了走线上。逻辑折叠的本质，是把电路布局从“一层楼”扩展成“多层楼”，把原本需要长距离横向走线的关键路径“折”起来，纵向叠放，从而大幅缩短信号传播的物理距离。\n　　而逻辑折叠只是华为多层级协同体系中的一个关键抓手。从华为此前公布的技术路线图来看，“韬定律”构建了一个贯穿器件、电路、芯片到系统的四层级优化体系。\n　　在最底层的器件层面，华为从优化晶体管的电阻、寄生电容入手，从物理底层最大限度压缩时间常数τ，打好地基。\n　　在电路层面，逻辑折叠技术突破传统平面布局的物理边界，把电路从单层“折”成双层乃至多层。\n　　在芯片层面，华为引入“软件、架构、芯片”的全栈协同设计，基于实际工作负载去调配指令流和数据流，让芯片只算必须算的东西，减少无效开销，把端到端的执行时间压到最低。\n　　在最顶层的系统层面，华为还定义了“灵衢总线”，重构计算系统互联协议，实现“超节点统一内存编址和原生内存语义”，让数据在不同计算单元之间来回交换时几乎不再有“堵车”的感觉。\n　　这四个层级不是一个一个去优化的线性组合，而是像齿轮一样咬合在一起。如果打个比方，传统的芯片优化路径，就像在一条越来越窄的窄路上拼命堆砌跑车。而“韬定律”把整个路线图拉到了更宽的维度上：器件、电路、芯片、系统协同演进，信号跑得更快、算得更聪明。\n　　“韬定律”的高端芯片目标\n　　“韬定律”能不能成立，最终看产品。\n　　何庭波在演讲中提供了一个关键数字：过去六年，华为基于这条路径已成功设计并量产了381款芯片，覆盖通信、计算、终端、车载等各个领域。这是华为“韬定律”理论能够站住脚的重要底气。\n　　真正让市场期待的，是今年秋天即将发布的新一代麒麟手机芯片。按何庭波的说法，这颗芯片将完整采用逻辑折叠技术，基于全新的自由逻辑设计理念，由单层扩展至双层，实现晶体管密度和系统性能的大幅跃升。\n　　何庭波的原话是：“我们取得了一系列仅靠先进制程工艺难以取得的进步。”这可能意味着华为走通了一条不同于台积电、三星、英特尔的独立路线。\n　　她还透露了一个更长远的目标：到2031年，基于“韬定律”的高端芯片，晶体管密度将达到1.4纳米制程的同等水平。这意味着华为将通过系统级的时间优化，实现与1.4nm工艺同等的集成密度和计算能力。\n　　这到底是不是一条走得通的路线？何庭波的原话是：“我们的解决方案走得通，走得远。我们新芯片的性能完全可以持续对标另外一条路径。”\n　　全球半导体产业的新技术浪潮\n　　如果“韬定律”可以被理解为从“空间”转向“时间”的范式转移，那么全球半导体产业的另一条主线，就是从“平面”走向“立体”。\n　　有趣的是，这两条线正在同一时间点上交汇。\n　　以先进封装、Chiplet异构集成和混合键合为代表的技术浪潮，正在以前所未有的速度和规模重塑芯片的性能边界。它们与“韬定律”的核心思路异曲同工：不依赖晶体管本身的无限微缩，而是通过更聪明的集成和互连方式，推动系统级性能的持续跃升。\n　　先看先进封装。如果说过去几十年，业界讨论“几纳米”就是讨论芯片的一切，那么从2024到2026年，讨论话题的重心正在快速向先进封装倾斜。根据Yole Group的数据，2025年全球先进封装市场规模约531亿美元，预计到2030年有望达到794亿美元，年复合增长率约8.4%。更令人吃惊的是2.5D/3D封装的增长速度：2023年至2029年间，其年复合增长率高达37%。\n　　为什么涨得这么快？原因简单粗暴：AI芯片需求爆了。以台积电CoWoS为代表的先进封装，把GPU核心和高带宽内存（HBM）紧贴在一起，信号传输距离从毫米级压缩到微米级，是AI大模型时代算力爆炸的“隐形底座”。数据显示，目前全球2.5D与3D先进封装产能仍供不应求，部分订单从下单到交货甚至超过一年，供应缺口高达约23%。全球头部厂商正在掀起扩产狂潮：台积电计划布局七座先进封装工厂，规划到2027年将年产能从130万片提升到200万片，增幅约53.85%。\n　　再看Chiplet（芯粒）。这项技术背后的逻辑是把一颗超大芯片拆成多个小芯粒，各自用最优制程做出来，再通过先进封装“粘”在一起，有点像“把一块大棋盘切成几块小拼图再拼回去”。Chiplet架构在AI芯片中已经大面积铺开，尤其对于国内芯片厂商来说，这项技术更具战略意义：它允许部分核心模块使用先进制程，而非关键的I/O、存储模块用成熟制程，有效弥补了先进制程受限的短板，实现了“用有限资源换系统级性能”。\n　　如果说Chiplet是“搭积木”，那混合键合就是决定这些积木能不能搭得稳、搭得密的那把“胶水”。混合键合的突破性在于：它完全不需要焊料凸块，直接让铜和铜在原子层级接触，实现芯片间铜-铜和氧化物-氧化物的直接键合。相比传统热压键合，混合键合带来的互连密度能提升一到两个数量级，寄生电容极低，信号延迟和功耗都大幅下降。\n　　这项技术被业界视为“后摩尔时代未来十年的必选技术路线”。从具体落地看，存储巨头们已经集体杀入。SK海力士和三星都在为下一代HBM高带宽内存铺路，预计混合键合将从HBM4开始引入，16层HBM的堆叠结构正在紧锣密鼓地验证中。混合键合设备市场的年复合增长率预计高达69%，远超半导体行业的整体增速。\n　　还有一个更前沿的方向：硅光互连与光电共封装（CPO）。\n　　信号传输的本质瓶颈，正在从芯片内部向芯片之间、乃至机柜之间的互连转移。传统的铜互连在高频率下损耗大、距离有限，越来越撑不住大规模AI集群的带宽需求。硅光互连的核心思路是用光代替电来传信号，速度更快、延迟更低、功耗大幅下降。\n　　台积电在2026年5月的技术论坛上高调披露了其“三层蛋糕”AI平台架构：底层是运算层（Compute），中间是封装集成层（CoWoS/SoIC），最顶层是“未来最重要的”光子互连层（COUPE）。COUPE技术通过3D异质集成方式，将电子芯片与光子芯片垂直堆叠，使得组件之间距离极近，大幅降低电耦合损耗。据台积电透露，今年已启动全球首款采用COUPE技术的200Gbps微环调制器的量产，比特误码率低于一亿分之一。相比传统铜线，COUPE可使系统能效提升4倍、延迟降低10倍；若与封装平台深度整合，能效甚至可提升到10倍，延迟降低20倍。\n　　国金证券在最新研报中明确指出：2026年是CPO的产业化元年。台积电、英伟达、博通等产业链核心玩家已经跑步进场，标志着“光进铜退”在AI数据中心的大规模落地正式拉开帷幕。\n　　结语\n　　往长期看，华为“韬定律”与整个产业技术演进的方向是高度一致的。不论叫“时间缩微”还是叫“先进封装”，背后的本质都是一个根本性的共识判断：芯片性能的提升，不能再只依赖“把晶体管做小”。\n　　真正的竞争正在转移到一组新的维度上：互连密度、信号延迟、系统协同、垂直堆叠、光互连。这些维度的组合效应，远比单纯缩小一个节点要复杂、也要广阔得多。用华为自己的话说，2026年到2035年，随着大量探索性技术的逐步产品化，晶体管的密度将持续提升，工作频率将持续增长，高性能芯片源源不断。\n　　何庭波在演讲的结尾，说了一句意味深长的话：“未来一定属于开放合作。在半导体演进的路径上，没有一家企业可以独自完成所有答案。在‘韬定律’的路径下，我们期待与全球科学家、工程师和产业伙伴紧密合作，共同推动半导体与电子产业持续发展。”\n　　芯片产业链太长、太复杂，没有一个国家、一家公司能包揽全链条。包括光刻机在内的半导体设备、封装基板的材料、EDA工具、CPO的标准体系……每一环都需要全球协作。华为提出“韬定律”，是在半导体行业寻找全新增长曲线的关键时刻，为世界提供一种兼容、开放、可供选择的中国方案。\n\n\n海量资讯、精准解读，尽在新浪财经APP\n\n责任编辑：凌辰","news_type":1,"symbols_score_info":{"TSMX":0.6,"AVGG":0.6,"ANV":0.6,"AVGO":1.6,"AVGX":0.6,"TSMY":0.6,"LINT":0.6,"NVDS.UK":0.6,"2NVD.UK":0.6,"07388":0.6,"NVII":0.6,"TSMZ":0.6,"INTC":1.52,"AVS":0.6,"NVDL":0.6,"NVDA":1.6,"NVDO":0.6,"SNVD.UK":0.6,"NVDG":0.6,"TSMG":0.6,"03145":0.6,"TSM":1.75,"TSMU":0.6,"AVGW":0.6,"NVD2.UK":0.6,"NVIW.SI":0.6,"04335":1.52,"07788":0.6,"AVL":0.6,"NVDU":0.6,"NVYY":0.6,"NVDX":0.6,"NVDQ":0.6,"STSM":0.6,"NVDS":0.6,"NVDY":0.6,"NVD3.UK":0.6,"3NVD.UK":0.6,"SOX":1.57,"NVDB":0.6,"INTW":0.6,"AVGU":0.6,"DIPS":0.6,"NVD":0.6,"NVDD":0.6,"NVDW":0.6}},"isVote":1,"tweetType":1,"viewCount":61,"authorTweetTopStatus":1,"verified":2,"comments":[],"imageCount":0,"langContent":"CN","totalScore":0}],"defaultTab":"following","isTTM":false}