芯片，过热了！

格隆汇09-11

AI芯片正在变得越来越大，也越来越热。过去几年，为了继续提升AI算力，芯片产业想出了很多办法。晶体管微缩越来越困难，就用Chiplet；单颗裸片装不下，就用CoWoS把多颗计算芯片放到一起；片上存储带宽不够，就不断增加HBM；芯片之间的数据传输成为瓶颈，又开始发展NVLink、UALink乃至CPO。但所有这些技术最终都把问题推向了一个越来越无法回避的物理约束：热。在2026年SEMICON ...

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Chen给出了一组数据，让人惊叹不已。按照其披露的技术演进预期，从2024年至2029年，CoWoS封装规模将从约3.3倍光罩尺寸扩大到超过14倍，单个封装中的计算晶体管规模可能增加约48倍，HBM总带宽增加超过34倍。与之伴随的，是AI系统和先进封装功耗快速提升。相关信息显示，台积电预计未来五年AI系统功耗可能增加约6倍，先进AI封装的功耗将从数百瓦逐渐迈向约4.1kW级别。AI芯片产业正在遇到一个越来越棘手的问题：芯片可以继续堆，HBM可以继续加，封装可以继续做大，但这些晶体管产生的热究竟怎么排出去？散热，正在从AI服务器的配套问题，逐渐变成决定下一代AI芯片还能不能继续扩张的底层技术问题。AI芯片，进入Thermal Scaling时代回头看过去几十年的半导体产业，性能提升很大程度上建立在Scaling之上。第一阶段是晶体管微缩（Transistor Scaling）。晶体管越来越小，从28nm、16nm一路走到7nm、5nm、3nm、2nm、埃米，单位面积能够容纳更多晶体管。但当先进制程越来越昂贵，单颗芯片尺寸又受到光罩极限等约束以后，产业开始寻找第二种扩展方式：封装扩展（Packaging Scaling）。Chiplet、2.5D、3D IC、CoWoS、HBM、Hybrid Bonding，本质上都在解决同一个问题：既然单颗芯片无法无限扩大，就把更多芯片放在一起。台积电今年公布的先进封装路线图显示，到2028年，14倍光罩尺寸的CoWoS计划可以整合约10颗大型计算芯片和20颗HBM堆叠；2029年还将进一步突破14倍光罩尺寸，并同步推进约40倍光罩规模的SoW-X系统级晶圆技术。但是封装继续扩展之后，一个新的物理约束开始变得越来越突出。一个封装里可以放10颗计算芯片，也可以放20颗HBM，但这并不代表这些芯片能够无限制地同时满负荷运行。最终决定性能上限的一个核心问题变成：这些晶体管产生的热，能不能及时带走。因此，AI芯片很可能正在进入第三种扩展阶段：热管理扩展（Thermal Scaling）。它解决的并不是“还能塞进去多少晶体管”，而是：同样的面积和体积里，究竟还能安全运行多少瓦计算。这会让AI芯片性能竞争出现一个非常值得注意的变化：我们不仅要关注单位面积晶体管数量，也不只有TB/s带宽、凸点间距和Die-to-Die带宽，还会越来越关注一个过去更多存在于热工程领域的指标：W/cm²，也就是单位面积能够处理多少瓦热量。在NVIDIA GTC 2026的一场液冷技术会议中，Supermicro披露，服务器机柜功率过去几年已经从约45kW迅速提高，而Vera Rubin参考架构单机柜可达到约227kW。按照其展示的规划，下一阶段甚至可能进入400—500kW级，长期进一步向兆瓦级机柜逼近。Supermicro同时表示，Vera Rubin要求100%液冷。一颗600W的GPU可以用大型散热器或者冷板来解决散热的问题，但如果一个封装最终整合十颗大型计算芯片和20颗HBM，功耗向数千瓦发展，传统散热路径的压力就会快速增加。2026年7月发表在《Applied Thermal Engineering》的一项2.5D封装热管理研究，就构建了包含环氧塑封材料和RDL的现实测试结构，在约948W总功率、400W/cm²热流密度环境下研究Chiplet之间的热耦合问题。论文就把“抑制不同Chiplet之间的热串扰”列为微流道冷却的重要目标。【1】因而现在，散热问题会不断向制造的上游移动。我们现在看到的趋势是：逻辑芯片、存储、先进封装和设备厂，正在同时把热管理往半导体制造环节内部搬。台积电押注Microchannel，散热正在逼近晶体管在SEMICON Taiwan 2026上，James Chen将微流道冷却（Microchannel Cooling）作为未来高功率AI先进封装的重要技术方向之一。TrendForce报道显示，其研究结构已经展示超过5kW级别的散热能力，用于应对未来4kW甚至更高功耗的先进AI封装。在讲微流道冷却技术之前，让我们先来看看当前的散热存在哪些痛点。回看过去几十年，芯片散热的基本思路其实没有发生根本改变，都是尽可能把热从硅片传递到外部，再通过空气或者液体带走。最早的数据中心主要依赖风冷。芯片产生热量以后，通过导热材料、热扩散盖和大型散热器把热传递给空气，再依靠风扇和机房空调排出。随着GPU进入数百瓦时代，直接液冷开始快速普及。典型冷板的散热路径大致是：硅片 → 导热界面材料 → 热扩散盖 → 导热界面材料 → 冷板 → 冷却液。与空气相比，液体能够承担更高的热流密度，但这里仍然存在一个无法消除的问题：芯片和冷却液之间隔着多个材料界面。而任何一个界面，都意味着额外的热阻。IBM关于先进芯片热管理的研究就指出，传统倒装芯片封装通常通过芯片背面向液冷板散热，中间需要铜盖和导热界面材料实现机械保护与热传导。减少一个导热界面，甚至直接让冷板更加靠近裸片，都可以继续降低热阻。IBM认为，层间冷却是唯一一种能够随芯片堆叠中芯片数量扩展的体积冷却解决方案（下图a），因此能够实现极高的3D集成度。由于芯片堆叠流体腔内流经的水冷液附近存在电气互连，因此需要特定的密封结构，例如环形结构。双相介质冷却可以降低这种复杂性。然而，即使在高压下，封装也需要提供结构完整性支撑（图 4b、c）。【2】a) 层间冷却拓扑结构示意图。b) 层间冷却模块。c) 层间冷却芯片堆叠的扫描电镜图像横截面，微通道壁上嵌入有TSV。（图源：IBM）因此，从工程逻辑看，既然外面的冷板距离晶体管还太远，就继续把冷却结构往硅片方向推进。Microchannel Cooling，也就是微流道冷却，正是在这种背景下开始受到重视。它的基本原理是：在靠近芯片的位置加工大量微米尺度流道，让冷却液直接经过高热流区域，从而缩短热从硅片进入冷却液的距离。事实上，微流道并不是什么突然出现的新技术。早在1981年，学术界就已经开始研究利用硅微流道为高热流密度芯片散热；2012年，DARPA启动ICECool项目，更明确提出把微流体冷却带进基板、芯片和封装内部。台积电也已经研究多年。2021年，台积电就曾公开一种面向3D IC的直接硅水冷方案：通过低温键合将带有沟槽和网格状冷却结构的硅盖板与逻辑芯片结合，让冷却水尽可能靠近芯片背面。其测试结构曾实现单颗SoC超过2600W的总散热功率，对应约4.8W/mm²的功率密度；进一步采用直接硅背面水冷后，演示功率密度超过7W/mm²。所以Microchannel真正的创新，并不只是“把水道做得更小”，而是把原本位于芯片外部的冷却结构逐渐搬进封装甚至硅片内部。值得注意的是，Microchannel Cooling本身也并不是一条单一的技术路线。一个关键分歧在于：微流道究竟应该做到多靠近硅片？2026年发表在Nature旗下《Communications Engineering》的一项研究选择了一条相对折中的路线。研究人员没有把微流道直接加工进半导体基底，而是将其嵌入封装基板，形成Direct-to-Package冷却。实验中，这套方案处理的热流密度达到约625W/cm²，只需要约2—4mL冷却液；相比环境空气冷却，其结温和热阻降低约6—7倍，相比传统带TIM的液冷散热器也降低约2—3倍。【3】直接封装冷却概念的设计和原型上图为所提出概念的示意图，下图为微流控基板和封装原型的组装示意图。（图源：Nature）另一条路线则更加激进——继续让冷却液向硅片内部靠近。2026年，KAIST与Georgia Tech研究人员展示了一种歧管式微流道冷却器，将微流体结构直接嵌入硅热测试芯片，并采用低于350℃的CMOS兼容工艺制造。在室温单相水冷条件下，该结构实验展示了超过2000W/cm²的芯片级热流密度，同时将结温控制在100℃以下，总压降仅7.8kPa。【4】而现在，Microchannel也已经不再只是实验室里的研究课题。微软此前已经测试了一套芯片内微流体冷却系统，直接在硅片背面刻蚀出微小流道，让冷却液尽可能贴近高温硅片流动。实验室测试显示，根据不同工作负载和系统配置，这套方案的散热效果最高可达到传统冷板的3倍，并将GPU内部硅片的最大温升降低65%。微软还利用AI识别芯片不同区域的热点分布，对微流道进行针对性设计，让冷却液更加精准地流向高热区域。微软已经开始研究如何把这项技术真正纳入芯片制造和数据中心部署。下一步，微软计划继续与晶圆制造和芯片合作伙伴推进Microchannel在未来自研芯片中的应用。把这些进展放在一起，会发现Microchannel正在经历一个很重要的变化：它正在从一项“散热技术”，逐渐变成一项“芯片技术”。而它的产业化也面临一个非常现实的矛盾：冷却液离晶体管越近，散热潜力越大；但冷却系统每向硅片靠近一步，制造难度、密封要求和可靠性挑战也会随之提高。如果继续沿着这条路线前进，散热技术大致可以形成这样一条演进路径：风冷 → 冷板液冷 → 封装内微流道 → 直接硅片冷却。HBM可能比GPU更怕热这种趋势并不限于计算芯片。当AI芯片进入2.5D先进封装时代以后，需要解决的已经不只是GPU或者AI ASIC自身产生的热。旁边的HBM，同样可能成为整个封装的散热瓶颈。HBM则是另一种结构。它不是一颗普通的平面DRAM，而是把多层DRAM裸片通过TSV垂直堆叠起来。随着HBM从早期的4层、8层逐渐发展到12层乃至16层，相当于越来越多的有源硅片被压缩在一个很小的立体空间里。这意味着HBM面临的热问题具有两个维度：一个是自身产生的热，另一个是旁边计算芯片传过来的热。这正是2.5D先进封装带来的一个新问题——热耦合。Vinci在2026年发布的一项2.5D AI加速器封装研究指出，现代AI加速器和HPC器件的功率密度已经经常超过1W/mm²，而先进2.5D封装正在将高功率AI ASIC与8—16颗HBM共同集成。由此产生的一个问题是热耦合：ASIC内部形成的局部热点会向相邻HBM横向传热，推高HBM结温，进而可能造成工作频率下降、性能降频以及存储器加速老化。研究展示的一个代表性封装由2颗AI加速器ASIC和8颗HBM组成，在最大功耗条件下，HBM结温已经接近100°C。【5】HBM温度持续升高之后，同样可能影响工作频率和系统性能，并加速存储器老化，最终影响整个AI加速器的可靠性。更麻烦的是，随着先进封装不断做大，这种热耦合还可能越来越复杂。过去芯片布局更多考虑的是信号距离、带宽、布线和封装面积。例如，把HBM尽可能靠近GPU，可以缩短信号路径，提高互连效率。但从散热角度来看，两颗高功率芯片靠得越近，又可能加剧彼此之间的热影响。于是一个新的矛盾出现了：电气设计希望芯片靠得更近，热设计却可能希望它们离得更远。因此，可以看到，过去HBM竞争更多围绕堆叠层数、容量和带宽，现在存储厂已经开始直接修改HBM内部结构来解决散热。2026年5月，SK海力士发布iHBM方案，在HBM封装内部加入集成冷却元件ICE（如下图所示）。这种采用电绝缘、高导热硅基材料制作的结构，会在HBM内部额外形成热传导路径。SK海力士称，该方案可以使热阻降低30%以上，并计划面向下一代高性能HBM应用。SK海力士公布的“iHBM解决方案”概念图（来源：SK海力士）三星也在做类似的事情。三星在COMPUTEX 2026展示的HBM4E/HBM5技术中加入了HPB，也就是热传导块。三星指出，负责HBM与GPU高速通信的Die-to-Die PHY已经成为基底芯片内部的重要发热区域，数据传输速度越快，局部发热越严重。因此HPB专门在这一高速接口附近构建额外热传导路径，把热量更快导出。三星目前正在HBM4E上验证这一技术，并计划在HBM5中采用。所有这些技术都在表明，冷却液正在越来越靠近晶体管。过去是在机房里冷空气；后来进入服务器；再后来进入冷板；现在开始进入封装；未来甚至可能直接面对硅片。散热技术的边界，也因此第一次真正进入了半导体封装内部。当散热进入芯片，新的半导体产业链来了但微流道能不能真正成为产业，并不取决于实验室里能不能给一颗芯片降温。真正困难的问题是，怎么把它稳定地制造出来。这也是今年SEMICON Taiwan上另一个非常值得关注的变化。德国工业激光与半导体设备厂商TRUMPF首次展示了一套面向AI芯片集成冷却的超短脉冲激光加工方案。按照TRUMPF 9月1日发布的信息，这套技术可以直接在芯片堆叠结构内部加工超细冷却微结构，公司的目标不是实验室原型，而是实现这些冷却微结构的工业化、低成本制造。这个信号的重要性其实不亚于台积电研究微流道本身。因为一项技术真正成为半导体产业，往往需要经历：架构设计 → 工艺开发 → 设备 → 材料 → 良率 → 大规模量产。当专门的设备厂开始为芯片集成冷却开发工业化工具时，说明散热正在从系统部件进入制造工艺。传统液冷产业链主要围绕冷板、CDU、泵、歧管、换热器等系统部件展开。但如果微流道进一步进入封装甚至硅片，产业链会发生明显变化。首先是微结构加工。微流道尺寸越来越小以后，可以采用激光，也可能涉及硅刻蚀、深刻蚀等半导体加工方式。结构尺寸、表面粗糙度、流道一致性都会直接影响流量和散热性能。其次是键合和密封。把微流道刻出来只是第一步。冷却液必须被可靠地封闭在距离昂贵AI芯片非常近的位置。封装层与微流道结构之间如何键合，长期热循环后会不会泄漏，界面材料是否发生腐蚀，都可能成为新的工艺挑战。再往下是流体分配结构。一个大型AI封装内部并不是每一个位置功耗都一样。未来的冷却系统很可能需要根据计算芯片、HBM和I/O Chiplet的位置设计不同的流量分配。如果局部流量不足，就会形成新的热点；如果流道过细，又会带来更高压降和泵送功耗。最后还有检测和可靠性。传统先进封装已经需要X-ray、声学检测、光学检测等手段检查凸点、空洞和键合问题。未来如果封装内部再增加液体通道，就还要解决流道完整性、密封、泄漏检测、颗粒污染，甚至冷却液与材料兼容性等问题。这也是微流道距离真正大规模应用仍然存在的重要门槛。2026年一篇关于Microchannel Cooling的综述就指出，冷却介质选择、微流道结构、基板材料以及制造复杂度，仍然是这类技术进一步产业化必须解决的问题。不同冷却液在导热性能、电绝缘性、黏度和化学稳定性等方面存在明显取舍。特别是“水离芯片越来越近”这件事，本身就意味着可靠性要求急剧提高。对于价值数万美元甚至更高的AI加速器而言，任何微小泄漏、堵塞或者材料兼容性问题造成的损失，都远远高于普通服务器。因此，嵌入式冷却并不会在短时间内彻底替代冷板。更现实的情况可能是一条逐渐向内迁移的技术路线：传统冷板仍然大量存在，但内部结构越来越精细；随后微流道进入热扩散盖或者封装；在最高功率密度的产品上，再进一步向直接硅片冷却发展。真正重要的不是哪一种技术最终胜出，而是：冷却正在新增一整套与半导体制造高度相似的工艺需求。结语HBM厂商开始增加专门热传导路径；先进封装开始研究微流道；设备厂开始开发微结构制造工具。这些看似零散的技术变化，实际上指向的是同一个趋势：热管理正在成为AI算力扩展的一部分。对于未来的AI芯片而言，水路结构将与电路线路（RDL、TSV、Power Delivery Network）一样，在晶圆与封测阶段被共同设计、蚀刻和键合。散热能力不再只是 AI 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