Cadence(CDNS.US)扩大与台积电(TSM.US)合作 AI加速先进制程芯片开发

智通财经04-23

智通财经APP获悉，全球电子设计自动化(EDA)龙头Cadence(CDNS.US)近日宣布扩大与晶圆代工巨头台积电(TSM.US)的战略合作，将人工智能芯片设计支持范围延伸至台积电N3、N2、A16及A14四大前沿制程。英伟达(NVDA.US)与Arm(ARM.US)等芯片生态关键玩家同步表达支持，一场围绕先进制程与AI驱动设计的产业协同正在加速落地。根据Cadence方面披露的信息，此次扩展...

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href=http://www.zhitongcaijing.com/content/detail/1432424.html><strong>智通财经</strong></a>\n\n\n</h4>\n\n</header>\n<article>\n<div>\n<p>智通财经APP获悉，全球电子设计自动化(EDA)龙头Cadence(CDNS.US)近日宣布扩大与晶圆代工巨头台积电(TSM.US)的战略合作，将人工智能芯片设计支持范围延伸至台积电N3、N2、A16及A14四大前沿制程。英伟达(NVDA.US)与Arm(ARM.US)等芯片生态关键玩家同步表达支持，一场围绕先进制程与AI驱动设计的产业协同正在加速落地。根据Cadence方面披露的信息，此次扩展...</p>\n\n<a href=\"http://www.zhitongcaijing.com/content/detail/1432424.html\">网页链接</a>\n\n</div>\n\n\n</article>\n</div>\n</body>\n</html>\n","isBrief":false,"type":0,"news_type":1,"symbol":"LU2471134879.HKD","symbol_name":"INVESCO GLOBAL EQUITY INCOME ADVANTAGE \"A\" (HKD) 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Development","themeId":null,"isJumpTheme":false,"ttsUrl":"https://static.tigerbbs.com/f12a8a3d6ed5c420e33dab993c7b525b","symbols_score_info":{"TSM":1.94,"TSMX":0.6,"CDNS":1.97,"TSMG":0.6,"STSM":0.6,"TSMU":0.6,"TSMY":0.6,"TSMZ":0.6,"03145":0.6},"content_text":"智通财经APP获悉，全球电子设计自动化(EDA)龙头Cadence(CDNS.US)近日宣布扩大与晶圆代工巨头台积电(TSM.US)的战略合作，将人工智能芯片设计支持范围延伸至台积电N3、N2、A16及A14四大前沿制程。英伟达(NVDA.US)与Arm(ARM.US)等芯片生态关键玩家同步表达支持，一场围绕先进制程与AI驱动设计的产业协同正在加速落地。根据Cadence方面披露的信息，此次扩展合作将为台积电上述先进工艺节点提供AI芯片设计所需的全套知识产权(IP)、可直接签核的端到端设计基础设施以及先进的认证流程。Cadence表示，这将显著减少芯片设计的迭代次数，并缩短从设计到量产的周期。在技术层面，Cadence已将代理式人工智能(Agentic AI)深度集成至芯片设计流程。在近期举行的CadenceLIVE 2026大会上，该公司发布了两款AI超级代理——ViraStack与InnoStack，支持从芯片规格制定到物理签核的端到端自动化设计。早期客户反馈显示，设计生产效率提升幅度达到3至10倍。与此同时，Cadence与Google Cloud达成合作，将ChipStack AI超级代理部署于云端平台，为大规模设计验证提供可扩展的算力支持。在模拟设计领域，Cadence已将代理式AI嵌入其Virtuoso Studio设计环境，支持从台积电N2到A14的模拟电路设计迁移。此外，3D-IC与芯粒(Chiplet)技术也是合作的重点方向之一，双方正共同推动多芯片堆叠与先进封装的设计流程创新。英伟达计算工程副总裁兼总经理Tim Costa在回应合作时指出：“下一代AI芯片日益增长的规模与复杂性，要求我们将加速计算与智能体人工智能集成到芯片设计周期的每一个环节。通过与Cadence的合作，英伟达正助力其设计团队及全球半导体生态系统，优化性能并加速全球最先进AI架构的交付。”Arm云AI业务部门市场推广副总裁Eddie Ramirez亦表示：“包括与Cadence及台积电在内的设计与制造伙伴之间的生态合作，对于推动下一代基于Arm架构的AI与高性能计算(HPC)部署基础设施至关重要。”值得注意的是，Cadence并非唯一与台积电深化协同的EDA供应商。在同一产业窗口期，新思科技与西门子EDA亦分别宣布扩大与台积电在先进制程领域的合作，覆盖3nm至A14工艺节点。台积电通过EDA联盟认证机制，与三大EDA厂商共同构建先进制程设计生态的趋势愈发明显。据行业研究机构测算，全球EDA市场规模在2026年预计达到207.8亿美元，其中AI EDA细分赛道将从2026年的42.7亿美元增长至2032年的158.5亿美元，年复合增长率高达24.4%，远超传统EDA市场增速。此次合作升级折射出AI芯片竞赛中的两个关键趋势。其一，产能稀缺背景下，“设计效率”成为差异化竞争的核心资产。台积电3nm产能目前已处于满载状态，优先供应英伟达、AMD、博通等头部云端AI及ASIC厂商;2nm产能更被谷歌、AWS、高通等全球科技巨头预订一空。在此背景下，能否利用高效EDA工具缩短设计迭代周期、抢先进入量产阶段，将直接影响芯片厂商的市场卡位。其二，先进制程竞赛已前移至埃米(Angstrom)时代。台积电A16制程预计于2027年量产，A14制程进一步向埃米级推进。EDA工具提前完成认证，意味着芯片设计公司可在制程正式量产前12至18个月启动设计工作，这对抢占AI芯片的市场时间窗口至关重要。分析人士指出，在AI算力军备竞赛持续升温的产业环境中，处于产业链上游的EDA工具与先进制程环节，正展现出更强的业绩确定性与议价能力。Cadence与台积电合作扩大的消息，或许只是这一价值重估进程的序幕。","kind":"news","is_publish_news":true,"is_publish_highlight":false,"is_publish_live":false,"is_publish_wemedia":null,"editions":null,"column":"","sentiment":"0","news_tag":"corporation","news_rank":0,"isVideo":false,"video":null,"symbols":[],"gpt_button":1,"need_auth":false,"need_login_tip":false,"code":"91000000","status":"200"},"commentList":[],"isCommentEnd":true,"newsSizeData":{"likeSize":0,"commentSize":0,"repostSize":0,"favoriteSize":0,"likeStatus":false,"favoriteStatus":false},"APP":{"userAgent":"Mozilla/5.0 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