SerDes，空前重要

格隆汇03-11

不知道你发现没有，从博通、Marvell 这样的 ASIC 设计服务厂商，到英伟达、AMD 等 GPU 巨头，再到 Credo、Astera Labs、Alphawave 等高速互联公司，几乎所有参与 AI 基础设施竞争的玩家，都在不断强化同一项能力：更快、更稳定、更高效的 SerDes。当 AI 训练和推理从单卡扩展到成百上千颗 GPU 的集群时，系统性能往往不再由单颗芯片决定，而是由节点之间的...

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importance","themeId":null,"isJumpTheme":false,"ttsUrl":null,"symbols_score_info":{"ANV":0.6,"2NVD.UK":0.6,"AVGO":1.96,"NVD":0.6,"DAMD":0.6,"VGT":0.8,"NVDX":0.6,"NVDG":0.6,"NVDD":0.6,"NVII":0.6,"AIYY":0.6,"NVIW.SI":0.6,"MRVL":1.94,"AMDU":0.6,"NVDQ":0.6,"NVDB":0.6,"AMDG":0.6,"AMUU":0.6,"NVDY":0.6,"NVDS":0.6,"AMDD":0.6,"NVDS.UK":0.6,"3NVD.UK":0.6,"NVDU":0.6,"NVD2.UK":0.6,"AMDY":0.6,"SNVD.UK":0.6,"NVDW":0.6,"NVD3.UK":0.6,"AMYY":0.6,"DIPS":0.6,"AMDL":0.6,"NVDA":1.92,"AMDW":0.6},"content_text":"不知道你发现没有，从博通、Marvell 这样的 ASIC 设计服务厂商，到英伟达、AMD 等 GPU 巨头，再到 Credo、Astera Labs、Alphawave 等高速互联公司，几乎所有参与 AI 基础设施竞争的玩家，都在不断强化同一项能力：更快、更稳定、更高效的 SerDes。当 AI 训练和推理从单卡扩展到成百上千颗 GPU 的集群时，系统性能往往不再由单颗芯片决定，而是由节点之间的数据交换效率决定。也正是在这种背景下，从 GPU、交换芯片到数据中心网络，再到 Chiplet 与 CPO 光互联，AI 基础设施的每一次演进，都在持续推高对高速互联的要求。而在所有互联技术之中，SerDes 正在逐渐成为最核心的底层能力。什么是SerDes？SerDes，即 Serializer/Deserializer（串行器/解串行器），本质上是一种用于高速数据传输的关键技术。它的核心作用，是在尽量减少 I/O 连接数量的前提下，实现芯片之间的大带宽数据交换。在集成电路系统中，芯片间通信可以采用并行传输，也可以采用串行传输。并行传输需要在芯片之间布置大量连接线，而串行传输通常只需要一对差分链路即可完成高速数据交换，因此更适合高带宽、长距离、低引脚数的系统设计。SerDes 的工作原理并不复杂：发送端将多路并行数据串行化，通过高速串行链路传输出去；接收端再将其恢复为原始的并行数据。正是依靠这种机制，现代芯片能够在有限封装和有限走线条件下，持续提升带宽密度。过去，SerDes 更像是芯片中的一个接口模块；但在 AI 时代，它正在上升为决定系统扩展能力的关键基础设施。从早期的 28Gbps NRZ、56Gbps PAM4，到今天的 112Gbps，再到即将规模落地的 224Gbps，SerDes 已经成为高性能计算、高速网络、汽车电子、移动终端和物联网 SoC 的通用底座，广泛支撑 PCIe、以太网、USB、MIPI、USR/XSR 等各类高速标准。也正因为如此，谁掌握了核心 SerDes 技术，谁就拥有了极高的技术壁垒和系统话语权。    ASIC设计服务厂商，无不是SerDes高手就拿这几年赚的盆满钵满的两大设计服务厂商博通和Marvell来说，他们之所以能拿走 ASIC市场80%的利润，是因为他们掌握了算力世界中唯一不可替代的稀缺资源——连接稳定性。它们的“连接霸权”，很大因素就来自SerDes能力所构建的系统级护城河。博通的 SerDes 以高性能和高集成度著称。以博通的Tomahawk 这类数据中心交换芯片为例，它本质上是一块“SerDes 密度怪兽”。例如Tomahawk 5（51.2T）最多可集成 64个Peregrine SerDes 核心，每个核心包含 8 路 106Gb/s PAM4 SerDes 收发器（并带 PCS）。而到了 Tomahawk 6（102.4T），博通进一步把高速互联推向更高代际。作为其 2026 年的重要产品，Tomahawk 6 将 224G SerDes 带入了更高密度、更高吞吐的交换平台。配合更强的铜缆传输能力，它使数据中心在不全面依赖更昂贵光互联的情况下，仍能维持高效的数据交换。Marvell的强项是协议覆盖和先进制程适配。其112G XSR/VSR SerDes专为 Chiplet 设计。它的 XSR（极短距）SerDes 功耗极低，是目前 D2D（芯粒互联）市场的标杆。Marvell在PCIe 接口上的 SerDes 进度快于博通，这使其在服务器内部的 HBM（高带宽内存）连接和存储控制器市场极具优势。例如，在刚结束的DesignCon 2026上，Marvell就率先展示了 PCIe 8.0 技术，这是目前业界唯一能在标准路径下实现 256 GT/s 传输的 SerDes。2025 财年博通的AI营收约200亿美元（同比增长 65%），预计2026年将达到250亿美元。Marvell的AI营收大约 39 亿美元，目标约超过50亿美元。博通的AI AISC市场份额大约在60%，Marvell在15%-20%。博通的 AI 收入几乎是 Marvell 的 4-5 倍，这源于它与 Google 长达十年的深度绑定，博通的霸权主要来自于 Google 的 TPU 订单。根据 2025 年底的数据，Google TPU 的出货量支撑了博通绝大部分的 ASIC 利润。而Marvell则通过拿下微软Maia芯片和亚马逊的新项目，实现了 ASIC 业务的翻倍增长。第三方机构Counterpoint Research预测，到2027年，博通仍将以约 60%份额领跑AI服务器计算ASIC设计合作伙伴市场。但是，值得注意的是，让博通不得不警惕的新玩家之一，是联发科。据悉，联发科成功切入谷歌第八代TPU（TPUv8x）设计，预计于2026年第四季开始贡献营收。谷歌与联发科合作设计芯片，前者负责运算单元（Compute Die）设计与高频宽记忆体（HBM）采购；后者负责输出入单元（I/O Die）设计、所有晶圆采购，以及后段封装整合。联发科之所以能在数据中心ASIC领域异军突起，接下Google或Meta的ASIC订单的关键，正是在于研发超过十年、能提高传输效率的SerDes IP技术。联发科现行112Gb／s SerDes DSP采PAM-4接收架构，在4纳米制程可实现超过52dB的损耗补偿能力，仍能维持低讯号衰减与高抗干扰特性，对资料中心与先进封装架构尤为关键。联发科专为资料中心应用打造的224G SerDes，并完成硅验证（silicon proven），技术成熟度获业界高度关注。联发科副董事长蔡力行表示，非常有信心2026年实现超过10亿美元的数据中心ASIC营收，并在2027年达到数十亿美元。分析师预测，联发科这波ASIC营收上修，应该还是来自谷歌的TPU订单。ASIC业务已成为联发科第二大营收来源。所以，从博通、Marvell 到联发科，都在说明同一个结论：ASIC 设计服务厂商，几乎无一不是 SerDes 高手。英伟达和AMD芯片巨头的Serdes代际演进不仅是ASIC 设计服务厂商，英伟达与 AMD 这样的 GPU 巨头，同样在持续强化自身的 SerDes 能力。以英伟达为例，其GPU之间的高速互联依赖自研的 NVLink。NVLink 的代际演进，本质上是 SerDes 速率升级与链路规模扩展的双重推进：一方面通过提升单条 SerDes 的传输速率，另一方面通过增加链路数量和优化互联拓扑，从而实现系统带宽的指数级提升。从 Ampere 架构到 Blackwell 架构，NVLink 所依赖的 SerDes 技术已经从 约 56Gbps 级别演进至 224Gbps 级别，使得单颗 GPU 的互联带宽实现跨代跃升。这种持续提升的高速互联能力，使 NVLink 成为英伟达 GPU 生态的重要护城河，也构成了其 AI 集群架构的核心优势。相比之下，AMD 的 SerDes 技术演进路径有所不同。AMD 的高速互联体系更多围绕其 Chiplet（芯粒）架构与 Infinity Fabric 协议展开，并在整体策略上更倾向于拥抱行业标准，例如 PCIe 与 CXL 等接口协议。在 AMD 看来，仅依赖私有互联协议很难在生态规模上与英伟达抗衡，因此它选择推动更开放的互联体系。为此，AMD 联合博通、微软、Meta 等公司发起了 UALink（Ultra Accelerator Link）联盟，试图构建一个面向 AI 加速器互联的开放标准。从技术角度来看，UALink 的目标同样是构建高带宽 GPU 互联，但与 NVLink 的封闭体系不同，它希望依托产业链成熟的 SerDes 技术与以太网生态，打造一个能够在规模上挑战英伟达互联体系的开放生态。这也说明，在 AI 算力竞争日益激烈的背景下，SerDes 已经不仅仅是芯片中的一个接口模块，而是决定整个 AI 计算平台扩展能力的关键技术。Serdes，也孕育了一帮初创互联公司当互联成为新的基础设施，一批专注于高速连接技术的公司也随之崛起。以 Credo、Astera Labs 和 Alphawave Semi 为代表的新兴厂商，正试图在 GPU 与交换芯片之外，建立属于自己的“互联赛道”。其中，Credo 是近年来增长最迅猛的高速互联公司之一。2026财年全年营收大概率落在约13.23–13.33亿美元区间，整体毛利率约在66%–67% 区间。已经连续多个季度实现三位数增长，这不仅显示出 AI 数据中心互联市场的爆发力，也显示了SerDes /互联芯片的毛利率普遍非常高。不同于博通那种重度依赖 DSP（数字信号处理）的方案，Credo的核心竞争力在于其模拟前端（Analog Front-end）优化。该公司以自研 112G/224G SerDes 技术为核心，围绕 Retimer 芯片和 AEC（有源铜缆）构建产品体系，主要解决 AI 服务器内部和机架级互联中的信号衰减问题。AEC（有源电缆）是Credo最成功的商业化路径。在 112G/224G 下，普通的铜线（DAC）传不动，光模块（AOC）又太贵，Credo 的 AEC 通过在电缆两端加入 SerDes/DSP 芯片，实现信号均衡和重定时，从而显著延长高速链路距离并降低误码率。另一家快速崛起的公司是 Astera Labs。Astera Labs 2025 财年营收 8.53 亿美元，同比增长115%，全年 GAAP 毛利率 75.7%。与 Credo 更偏“物理链路修复”的策略不同，Astera Labs 的核心定位是 智能连接平台。其产品围绕 PCIe 和 CXL 生态展开，包括 Aries 系列 PCIe/CXL Retimer、Scorpio Fabric Switch 以及 Taurus 智能电缆模块等。这些产品本质上是将 SerDes 和 DSP 技术与协议层软件结合，使系统能够在复杂拓扑结构下保持稳定的高速通信。随着 AI 服务器架构从单节点计算向 rack-scale 架构演进，这类“协议感知型互联芯片”需求迅速增加。Astera Labs 的业绩增长也非常惊人：公司 2025 年全年营收达到 8.53 亿美元，同比增长 115%，显示出高速互联市场的巨大潜力。Alphawave Semi的商业模式则更偏向SerDes IP与连接子系统供应商。该公司长期专注于高速 SerDes 与接口 IP 的研发，并将其封装为可直接集成到 SoC 或 ASIC 中的连接子系统，例如 224G SerDes、UCIe chiplet 接口以及高速 PHY IP。这使得 Alphawave 能够向不同的芯片厂商提供高速互联能力，而无需参与整颗芯片设计。随着 Chiplet 架构和先进封装逐渐普及，SerDes IP 的需求也在快速增加。值得注意的是，Alphawave 的技术价值也吸引了产业巨头的关注，2025 年高通宣布以约24亿美元收购 Alphawave Semi，正是为了加强其在数据中心和高速互联领域的布局。Credo 和 Astera Labs 的崛起证明了，在巨头转身缓慢的缝隙里，谁能解决 AI 集群最头疼的功耗与信号衰减问题，谁就能在万亿级市场中切割出属于自己的肥美领地。IP“军火商”的转型在这场由 AI 驱动的互联技术竞赛中，变化的不只是芯片公司本身，传统的 EDA/IP 厂商也正在悄然调整自身的战略重心。一个典型案例是新思科技（Synopsys）。近年来，Synopsys逐步弱化自有处理器业务，并将资源更多集中在 高速接口与互联 IP上，例如 SerDes、PCIe、CXL、UCIe 等关键技术。其出售 ARC 处理器业务，某种程度上也反映出一个趋势：随着 RISC-V 架构的快速崛起，通用处理器 IP 正在逐渐“平民化”，越来越多公司能够获得成熟的 CPU 设计能力，处理器本身不再是最稀缺的资源。相比之下，在 Chiplet（芯粒）架构逐渐成为主流的背景下，真正变得稀缺的是 高速互联技术。当一颗系统级芯片被拆分为多个 die 时，芯片内部的 die-to-die 互联就必须依赖极短距离、超低功耗的 SerDes 技术。以UCIe为代表的新一代标准，本质上正是为 Chiplet 时代打造的高速互联底座。在这种趋势下，EDA/IP 厂商的角色也在发生变化。它们不再只是传统意义上的设计工具供应商，而更像是产业链中的 “技术军火商”：通过提供成熟的 SerDes、PCIe、CXL、UCIe 等接口 IP，让没有深厚模拟电路和高速接口设计能力的 ASIC 厂商，也能够在较短时间内集成先进的互联能力。换句话说，在 AI 芯片竞争愈发激烈的今天，并不是每一家 ASIC 公司都必须从零开始设计 SerDes。只要购买成熟的接口 IP，并结合先进封装和系统设计能力，就可以快速构建出具备高带宽互联能力的芯片系统。这种模式大大降低了 AI 芯片设计的门槛，同时也让 Synopsys、Cadence 等 IP 厂商在新一轮计算架构变革中获得了新的增长空间。448G已经鸣枪，CPO正在合围如果说224G是当前AI数据中心互联的主流节点，那么448G SerDes已经成为产业链下一阶段的竞争焦点。在芯片与互联领域，多家厂商正在推进448G相关技术。Marvell 已展示 448G SerDes IP，并同步演示 256GT/s 的 PCIe 8.0 SerDes，其 ×16 配置理论双向带宽可达到 1TB/s。这些技术主要面向 AI 交换芯片、GPU直连等高带宽场景，目前已进入工程样片阶段，为未来量产奠定基础。在GPU厂商方面，英伟达也已明确下一代Rubin平台将采用 448G SerDes。配合第六代 NVLink 交换架构，单 GPU 的互联带宽预计可达到 3.6TB/s，而在 72 GPU 的 NVLink 域中，总带宽可扩展至 260TB/s。这类架构意味着 GPU 集群将能够在更大规模上进行算力调度，而448G SerDes正是支撑这一带宽跃迁的关键技术。当速率迈向 448G，电信号在传统铜线中的传输已触及物理极限，“光进铜退”不再是预言，而是架构级的必然选择。SerDes将是CPO 的起点。CPO（光电共封）的本质是将原本在板级长距离传输的电信号，尽可能提前转化为光信号。光学引擎离芯片越近，预留给电链路的裕量就越小。这就对 SerDes 的抖动、线性度及误码率提出了近乎苛刻的要求。CPO 绝非简单的以光替电，而是一场涵盖激光源集成（如博通推崇的 ELS 外置方案）、热设计、封装耦合与良率的复杂系统工程。SerDes 能力越强，电路径越短，系统裕量就越可控。 这种“以强制弱”的能力，正是博通与 Marvell 能在 CPO 领域保持绝对领先的底层逻辑。站在产业链的视角来看，无论是448G的实现还是CPO的商用，都在倒逼整个互联生态进行配套升级。448G PAM4 信号的验证难度远高于上一代技术，对信号完整性、误码率以及通道建模提出了更严格要求。因此，测试测量厂商也开始布局完整的448G验证体系。例如 Keysight、Anritsu、Tektronix 和 Teledyne LeCroy等厂商都推出了面向448G PAM4的全链路测试方案，覆盖发射机SNDR、RLM、信道S参数以及误码率等关键指标。其中，安立还与鸿腾精密合作完成了 448G Twinax线缆的信号完整性验证，进一步完善了高速互联的测试生态。从更宏观的角度来看，448G不仅是一次SerDes速率升级，更是整个AI互联体系的下一代技术基石。当模型规模继续扩大、GPU集群规模不断增长时，只有不断提升SerDes速率并优化互联架构，才能支撑未来AI算力系统的带宽需求。小结某种意义上说，AI算力革命的背后，其实是一场高速互联革命。AI时代，算力决定上限，而SerDes决定规模。","kind":"highlight","is_publish_news":true,"is_publish_highlight":false,"is_publish_live":false,"is_publish_wemedia":null,"editions":null,"column":"","sentiment":"0","news_tag":"","news_rank":0,"isVideo":false,"video":null,"symbols":[],"gpt_button":0,"need_auth":false,"need_login_tip":false,"code":"91000000","status":"200"},"commentList":[],"isCommentEnd":true,"newsSizeData":{"likeSize":0,"commentSize":0,"repostSize":0,"favoriteSize":1,"likeStatus":false,"favoriteStatus":false},"APP":{"userAgent":"Mozilla/5.0 AppleWebKit/537.36 (KHTML, like Gecko; compatible; ClaudeBot/1.0; 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