HBF、HMC等四大存储，谁能力敌HBM

半导体产业纵横01-05 17:59

HBM（高带宽内存）作为当前AI加速器GPU的核心配置，凭借垂直堆叠的薄DRAM芯片结构，以超高数据带宽为AI训练与推理提供了关键支撑，成为AI算力爆发的重要基石。然而，HBM存在两大显著短板：一是成本居高不下，其价格较普通DDR内存高出一个数量级；二是容量增长受限，受限于DRAM内存密度缩放的技术瓶颈，即便如英伟达Blackwell GPU搭载8个24GB HBM3e芯片堆栈（总容量192GB）...

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HBM?","themeId":null,"isJumpTheme":false,"ttsUrl":null,"symbols_score_info":{"NVDD":0.6,"NVDA":1.87,"NVDY":0.6,"NVD2.UK":0.6,"NVDS.UK":0.6,"NVD":0.6,"3NVD.UK":0.6,"NVDS":0.6,"NVIW.SI":0.6,"NVDU":0.6,"2NVD.UK":0.6,"SNVD.UK":0.6,"NVDX":0.6,"NVD3.UK":0.6},"content_text":"HBM（高带宽内存）作为当前AI加速器GPU的核心配置，凭借垂直堆叠的薄DRAM芯片结构，以超高数据带宽为AI训练与推理提供了关键支撑，成为AI算力爆发的重要基石。然而，HBM存在两大显著短板：一是成本居高不下，其价格较普通DDR内存高出一个数量级；二是容量增长受限，受限于DRAM内存密度缩放的技术瓶颈，即便如英伟达Blackwell GPU搭载8个24GB HBM3e芯片堆栈（总容量192GB），也难以满足模型规模爆炸式增长、上下文长度拓展及AI视频生成带来的海量内存需求。在此背景下，开发成本更低、容量更大的替代技术成为产业共识，类HBM技术阵营加速崛起，推动AI存储赛道进入多元化竞争时代。01SPHBM4：标准封装重构HBM应用边界JEDEC固态存储协会近期宣布，接近完成SPHBM4标准制定（\"SP\"即\"Standard Package\"标准封装）。作为HBM4的衍生技术，SPHBM4沿用了与HBM4完全一致的DRAM芯片与堆叠架构，在单堆栈容量上保持同等水平，核心差异在于接口基础裸片（Interface Base Die）的设计优化——可直接搭载于标准有机基板，而非传统HBM4依赖的硅基板，彻底改变了HBM的物理集成方式。在性能参数方面，HBM4堆栈采用2048位接口，较此前1024位接口实现翻倍，这是自2015年HBM技术问世以来的最大突破；而SPHBM4则将单堆栈接口位数降至512位，通过提升工作频率与采用4:1串行化技术，实现了与HBM4相当的数据传输速率，同时放宽了有机基板所需的凸点间距，降低了封装难度。更重要的是，有机基板布线赋予SPHBM4更长的SoC到内存通道支持能力，使其能够通过增加堆栈数量进一步提升总内存容量，为高容量需求场景提供了新的解决方案。值得强调的是，SPHBM4绝非\"低成本版HBM\"或\"降配替代方案\"，其存储核心性能与HBM4一脉相承，核心价值在于打破了HBM\"高价、仅限AI加速器专用\"的应用局限。随着标准落地，HBM技术有望拓展至CPU、网络芯片、云端ASIC等更多场景，推动市场规模实现实质性扩容。对于SK海力士、三星电子、美光三大存储巨头而言，SPHBM4与现有HBM共用DRAM芯片的特性，使其能在保持高端技术竞争力的同时，收获新增市场需求，而封装制约的缓解也将让大规模稳定供应能力转化为新的竞争优势。02HBF：高带宽闪存开启容量竞赛新篇章HBF（High Bandwidth Flash，高带宽闪存）结构与堆叠DRAM芯片的HBM类似，是一种通过堆叠NAND闪存而制成的产品。与DRAM相比，NAND闪存的容量密度优势显著，相同占用空间下，NAND容量可达DRAM的10倍，这一特性完美契合AI场景对大容量存储的迫切需求。HBF通过硅穿孔（TSV）技术实现多层NAND芯片垂直堆叠，采用先进3D堆叠架构与芯片到晶圆键合技术，构建了密集互连的存储结构。在性能与容量平衡上，HBF展现出突出优势：每个封装可堆叠多达16个NAND芯片，支持多NAND阵列并行访问，带宽可达1.6TB/s至3.2TB/s，与HBM3处于同一水平；同时，HBF以相近成本实现了远超HBM的容量——单堆栈容量最高可达512GB，8个堆栈即可实现4TB总容量，是HBM的8-16倍。此外，HBF打破传统NAND设计，实现独立访问的存储器子阵列，超越传统多平面方法，进一步提升了并行访问能力与吞吐量。不过，受限于NAND闪存的固有特性，HBF延迟高于DRAM，因此更适用于读取密集型AI推理任务，而非延迟敏感型应用。尽管尚未量产，但HBF已吸引产业巨头纷纷布局：2025年2月，SanDisk率先推出HBF原型并成立技术顾问委员会；同年8月，SanDisk与SK海力士签署谅解备忘录，推进规格标准化与生态建设，计划2026年下半年交付工程样品，2027年初实现商用；三星电子已启动自有HBF产品的概念设计，Kioxia在2025年FMS上展示了单模块容量5TB、带宽64GB/s的原型产品；国产厂商亦不甘落后，目前也正在切入HBF市场，其产品契合AI\"云-端协同\"趋势，为端侧AI推理提供高带宽、大容量支撑，助力AI终端应用落地。03HBS存储：终端AI的低成本高性能选择在HBM主导数据中心AI场景的同时，SK海力士针对智能手机、平板电脑等终端设备的AI算力需求，正在研发高带宽存储（HBS）技术，旨在攻克终端AI的存储性能瓶颈。HBS采用垂直导线扇出（VFO）封装工艺，将最多16层DRAM与NAND芯片垂直堆叠，通过直线直接连接芯片的方式，替代传统弯曲导线连接，大幅缩短了电信号传输路径（仅为传统内存的1/4以下），有效减少信号损耗与延迟，同时支持更多I/O通道。性能层面，VFO封装技术使HBS的能效提升4.9%，封装厚度减少27%，仅增加1.4%的散热量，实现了性能与形态的优化平衡；成本层面，HBS无需采用硅通孔（TSV）工艺，芯片制造无需穿孔，显著提升了良率并降低了生产成本，为终端设备厂商的采用提供了便利。尽管SK海力士尚未公布HBS的具体量产时间表，但该技术有望为终端设备带来更强大的本地AI处理能力，推动AI应用从云端向终端普及，重塑终端智能生态。04HMC存储：经典技术的差异化回归HMC（Hybrid Memory Cube，混合内存立方体）由美光与英特尔联合开发，最初旨在解决DDR3的带宽瓶颈，其核心结构是通过3D TSV技术将4个DRAM Die连接到堆栈底层的逻辑控制芯片。与HBM相比，HMC省去了中介层（Interposer），直接通过ABF载板实现互联，结构更简洁，延迟更低，但带宽能力通常弱于HBM，且对载板走线密度和系统级设计能力提出了更高要求。在HBM推出并成为JEDEC行业标准后，HMC曾逐渐边缘化，美光于2018年宣布放弃该技术并转向HBM。然而，随着AI存储对成本与差异化的需求日益凸显，HMC再次进入产业视野。成本与功耗维度上，HMC因无需中介层，规避了HBM因interposer和先进封装带来的良率压力，制造成本更低，供应链可控性更强，尽管其极限带宽和能效密度不及HBM，但功耗密度相对更高、系统设计复杂度上升的代价，在特定场景下可通过差异化优化弥补。未来，HMC有望在定制化AI系统中找到立足之地，成为算力、存储与先进封装深度融合的重要选项。如今，AI产业正告别单一HBM主导的时代，迈入技术路线多元化的新阶段。无论是英伟达推动的新型DRAM模组SOCAMM，还是以HBF为代表的3D NAND垂直堆叠架构，亦或是SPHBM4、HBS、HMC等差异化技术，AI存储的竞争核心已从单一技术性能比拼，转向成本、量产能力与系统级整体效率的综合较量。未来市场格局将呈现清晰的差异化分工：HBM仍将主导通用AI加速卡与高端HPC场景，凭借极致带宽满足核心算力需求；SPHBM4将拓展HBM的应用边界，渗透至更多通用计算场景；HBF将在AI推理等大容量、高带宽需求场景占据优势；HBS将赋能终端AI设备，推动智能终端普及；HMC等定制化方案则将在特定AI系统中实现差异化落地。随着各类技术的持续迭代与生态完善，AI存储赛道将迎来更为激烈的竞争与创新，为AI产业的持续爆发提供坚实支撑。","kind":"news","is_publish_news":true,"is_publish_highlight":false,"is_publish_live":false,"is_publish_wemedia":null,"editions":null,"column":"","sentiment":"0","news_tag":"","news_rank":0,"symbols":[],"gpt_button":0,"need_auth":false,"code":"91000000","status":"200"},"commentList":[],"isCommentEnd":true,"newsSizeData":{"likeSize":0,"commentSize":0,"repostSize":0,"favoriteSize":0,"likeStatus":false,"favoriteStatus":false},"APP":{"userAgent":"Mozilla/5.0 AppleWebKit/537.36 (KHTML, like Gecko; compatible; ClaudeBot/1.0; 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