从CoWoS到CoPoS：台积电掀起一场席卷芯片产业链的“先进封装变革”

智通财经2025-07-03

智通财经APP获悉，华尔街金融巨头摩根士丹利近日发布研报称，“芯片代工之王”台积电(TSM.US)已经启动建设310 mm² Panel-Level chiplet先进封装试产线(即CoPoS先进封装体系)，并带动ASE等半导体设备与先进封装设备巨头们将FOPLP尺寸同步收缩至300/310 mm²，意味着“圆片级CoWoS向面板级CoPoS先进封装”的封装超级更新迭代正式进入投资与初步试制造期。...

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CoPoS相关半导体设备交付与安装调试、2027年工艺上线、2027年中进入大规模设备投资决策期以及初步流片。CoPoS先进封装体系借鉴 CoWoS 的硅插硅技术栈，但在基板形态、高端半导体设备链与良率瓶颈上做了系统级调整，用更加强劲的性能天花板以及更易于扩张的产能，更大范围满足全球愈发庞大的AI算力需求。对英伟达、AMD以及博通、迈威尔科技等AI/HPC超级客户而言，CoPoS提供更大规模的先进封装I/O与HBM堆叠数，极大程度缓解先进封装产能供不应求与初步流片、芯片制造成本高企。就“性能上限”角度来看，CoPoS的面板级面积 + HBM堆叠组合能带来比现行CoWoS先进封装更大的带宽/容量扩增，因而对聚焦超大模型训练/推理体系的AI芯片而言具备更高性能天花板。从业绩增长与估值扩张角度来看，整个芯片产业链有望迎来大举增长。对于英伟达、AMD以及三大EDA巨头来说，有望通过供给侧产品更新迭代推动更大规模终端需求，尤其对于AI芯片霸主英伟达来说有望更大程度满足堪称“星辰大海”的AI算力需求;半导体高端设备与芯片原材料链因CoPoS面板化则即将迎来新一轮超大规模设备资本支出，尤其是对于激光切割、面板光刻、真空贴合、干膜封装等领域的全球最顶级半导体设备厂商，关键设备在于Panel-level 直写光刻、激光切割以及面板贴片。从圆片到面板：台积电领衔“CoPoS革命”CoWoS(Chip-on-Wafer-on-Substrate)先进封装流程集中于在300mm圆片硅中介层 (interposer) 上首先完成再布线与 TSV，然后将逻辑/存储裸片贴装于上，再整体键合到 BT/ABF 有机基板，由于圆片有效面积十分有限，大核心芯片+多HBM占位后，单片产出仅 3-4 颗，良率则跟随面积下降，最终导致单颗成本较高，产能长期受限，且性能天花板开始触及上限。CoPoS(Chip-on-Panel-on-Substrate)流程集中于将硅中介层或再布线层移到矩形面板 (PLP)上(典型为310 mm × 310 mm)，先制程成大面积嵌硅RDL，再贴装核心chiplet芯粒/HBM，最后与有机基板组装。CoPoS追求一次封装更多chiplet芯粒、更高HBM堆叠数，面向1nm及以下超先进制程以及下一代AI芯片性能跃升。但翘曲与角缘涂膜均匀性是新挑战。因此基于CoPoS的面板可利用率高、单板面积约等于圆片3-5 倍，叠加潜在产能提升 ×2—×3、单位面积成本降低约20-30%，半导体设备链可能需重新适配(主要集中于大型激光分割、直接成像光刻以及真空贴片机)。大摩表示，对于芯片产业链而言，从 12-inch 晶圆级设备跨到PLP相关原材料与设备是一轮全新的超大规模CAPEX周期，半导体设备巨头们(比如Disco、Ulvac、Screen HD以及Canon)有望获得增量订单，堪称重大结构性增长机遇。CoPoS与AI算力随着ChatGPT风靡全球以及Sora文生视频大模型重磅问世，叠加AI领域“卖铲人”英伟达连续多个季度无与伦比的业绩，意味着人类社会迈入AI时代。在5月底的英伟达业绩会议上，黄仁勋极度乐观地预测Blackwell系列将创下史上最强劲AI芯片销售纪录，推动人工智能算力基础设施市场“呈现出指数级别增长”。“如今，每个国家都将AI视为下一次工业革命的最核心——一个为全球每个经济体不断生产智能以及关键基础设施的新兴产业，”黄仁勋在与分析师们的业绩讨论表示。推理端带来的AI算力需求堪称“星辰大海”，有望推动人工智能算力基础设施市场持续呈现出指数级别增长，“AI推理系统”也是黄仁勋认为英伟达未来营收的最大规模来源。在当下以AI芯片为核心的“带宽-算力”AI基础设施史无前例竞赛中，圆片级CoWoS已把英伟达AI GPU先进封装推进到至少6颗HBM存储系统、总带宽3.9 - 4.8 TB/s的极限，比如CoWoS-S 受限于 120 × 150 mm 以内的硅中介层尺寸。而面板级CoPoS 通过把承载面积放大到典型的310 × 310 mm，可容纳多达10-12颗下一代HBM——HBM4与更多 chiplet芯粒，理论峰值带宽有望突破13-15 TB/s，存储容量至少翻倍。更大规格的面板让GPU/CPU chiplet、光学 I/O Die、专用AI 加速IP可以更大规模封装集成，指数级缩短互连，大幅降低整体延迟和功耗，因此，就下一代AI芯片性能以及满足算力需求而言，CoPoS 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